I am currently involved in the following projects and activities:
General Chair: MPLR 2020
Member of the BDVA PPP Technical Committee
Individual Member of the RISC-V J Working Group
(PI, Technical Coordinator, EPSRC/Optrak Ltd.)
In this project we research transparent hardware acceleration of vehicle routing algorithms.
Bridging oneAPI to managed programming languages
(PI, Technical Coordinator, Intel Research Council)
In this project we provide interoperability between oneAPI and TornadoVM and high performance optimizations for the Intel platform.
(PI, Technical Coordinator, EU Horizon 2020, 957286)
The ELEGANT project aims to develop a novel software solution that addresses key challenges facing IoT and Big Data: interoperability, reliability, safety and security. Some of the key innovations of the proposed framework are lightweight virtualisation, automatic code extraction compatible with IoT and Big Data frameworks, intelligent orchestration, dynamic code motion and advanced code verification and cybersecurity mechanisms.
(PI, Technical Coordinator, EU Horizon 2020, 780245)
In this project we will research and develop end-to-end solutions for dynamic and automatic
exploitation of heterogeneous hardware on cloud-deployed Big Data stacks.
Beehive aims to provide a state-of-the-art hw/sw co-designed stack that will enable
researchers to perform vertical research (from the application code down to the
hardware; real or simulated).
We target a variety of programming languages, runtimes and architectures.
Please checkout Beehive's github pages for further information about the individual components here.
(Co-I, EU Horizon 2020, 732366)
In this project we aim to develop hyperscale JVMs on top of aggregated cloud resources. We plan to extend memory allocation and GC algorithms in NUMA settings able to handle TBs of memory.
PAMELA: A Panoramic View of the ManyCore Landscape In this project we focus on low-power heterogeneous execution of JVMs. We mainly target demanding portable Computer Vision applications implemented in Java and other programming languages. Heterogeneous execution (GPUs, FPGAs, etc.), hw/sw co-designed optimizations, scheduling, etc., on ARM and x86 architectures are explored.